A Level Computer Science OCR Practice Exam 2025 – Complete Study Resource

A half adder is a combinational logic circuit specifically designed to perform the addition of two single-bit binary numbers. It takes two inputs—which represent the bits to be added—and produces two outputs: the sum and the carry. The sum output represents the least significant bit of the result of the addition, while the carry output signifies whether there was an overflow to the next higher bit due to the addition of two 1s.

The design of a half adder typically employs an XOR gate for the sum and an AND gate for the carry, illustrating its fundamental function in binary addition. Since it directly processes two inputs and generates two specific outputs, it fits the criteria of having two inputs and two outputs effectively.

Other options either represent circuits that do not adhere to the specified number of inputs and outputs or have different functionalities. For example, a full adder has three inputs and two outputs; a D-type flip-flop has one input for data and one clock input, but it produces one output; and a multiplexer typically takes multiple inputs and selects one output based on control signals.